1. Field of the Invention
The present invention generally relates to a highspeed scanning type radio receiver. More specifically, the present invention relates to a radio receiver capable of scanning a plurality of channels separated from each other by a preselected frequency for every several channels, and of scanning then for every 1 channel to search a correct frequency upon detection of a signal, thereby stopping the scanning operation.
2. Description of the Prior Art
In radio receivers employing frequency synthesizer type electronic channel selector, the scanning operation is carried out for every 1 channel to perform the channel search operation.
FIG. 1 schematically shows a basic circuit arrangement of an FM radio receiver. This FM radio receiver is arranged with an antenna 10, a radio receiving unit 12 containing a converter unit for converting a frequency of an FM radio signal received from the antenna 10 into an intermediate frequency signal, a frequency discriminator 14 for converting a change in the frequencies of the intermediate frequency signal derived from the radio receiving unit 12, into a change in voltages, and a squelch circuit 16 for detecting whether or not the received signal is present based upon the output voltage from the frequency discriminator. The FM radio receiver further includes a window detector 22 for detecting whether or not a voltage corresponding to the center frequency of the intermediate frequency signal is output from the frequency discriminator 14, an audio frequency amplifier 18 for amplifying the output signal from the frequency discriminator 14, a speaker 20 for outputting the FM sound derived from the audio frequency amplifier 18, a frequency synthesizer 24 containing a phase-locked loop (PLL) circuit, a microcomputer (CPU) 26 for controlling operations of all circuit units, and a keyboard 28 for instructing the frequency synthesizer 24.
Referring now to FIG. 2, the normal scanning method of this FM radio receiver shown in FIG. 1 will be described. It should be noted that FIG. 2 represents an operation flow of the CPU 26 for executing the normal scanning operation.
During the normal channel scanning operation, the CPU 26 sends PLL data about a certain channel to the frequency synthesizer 24. The frequency synthesizer 24 synthesizes a preselected frequency based on the PLL data and then sends the synthesized frequency signal to the radio receiving unit 12. The radio receiving unit 12 mixes the synthesized predetermined frequency signal with the FM signal received via the antenna 10 by this radio receiving unit 12, thereby converting the frequency of the FM signal into the desirable intermediate frequency. The resultant intermediate frequency signal derived from the radio receiving unit 12 is supplied to the frequency discriminator 14. Then, the frequency discriminator 14 converts the intermediate frequency signal into a voltage signal in accordance with the frequency-voltage converting characteristic, and supplies the voltage signal to the squelch circuit 16 and the window detector 22. The squelch circuit 16 judges that the FM signal is received when, for instance, noise is lowered, thereby producing a squelch control signal (simply referred to as "SC" signal hereinafter). The window detector 22 generates a window signal (simply referred to as "WC" signal hereinafter) when the voltage corresponding to the center frequency of this intermediate frequency signal is detected.
In the normal scanning operation of FIG. 2, the CPU 26 starts an SC signal detecting timer (not,shown in detail) so as to detect the SC signal derived from the squelch circuit 16 (step S1), thereby judging whether or not the SC signal is produced from the squelch circuit 16 (step S2). If no SC signal is detected and the SC detecting timer is not timed out (step S3), the scanning operation is returned to the previous step S2.
Otherwise, if the SC signal is detected at the step S2, then the CPU 26, judges whether or not the WD signal is produced from the window detector circuit 22 (step S4). When the window signal is detected, the CPU 26 makes such a judgement that the FM signal is received in this scanned channel, and ceases this normal scanning operation. Otherwise, if no window signal is detected, then the CPU 26 sends the PLL data about the next channel to the frequency synthesizer 24 (step S5). When the SC signal detecting timer is brought into the time out state, the CPU 26 supplies the PLL data about the subsequent channel to the frequency synthesizer 24, so that the channel searching operation for the subsequent channel is commenced. As previously described, the scanning operation of the normal scanning operation is sequentially performed for every 1 channel.
In other words, since the channel scanning operation is sequentially carried out for every 1 channel in the conventional radio receiver, there is a drawback that the entire scanning speed is low, namely a lengthy channel scanning time is required to select the desired channel.